In the process of preparation technology of semiconductor devices, with the rapid development of ultra large scale integrated circuits, chip dimensions get smaller and smaller as the integration degree of chips gets higher and higher. In the process of chip preparation technology, Critical Dimension (CD) is smaller and smaller with the development of technology generation, so the requirement to photolithography technology is higher and higher. In advanced photolithography technology, because of the reduction of dimension of exposure patterns, it is needed to make Optical Proximity Correction (OPC) to photomask pattern in advance, so as to compensate optical proximity effect produced by limited resolution of an optical system. However, in traditional advanced integrated circuit technology, an optical model for making a model based OPC to gate photomask pattern is created based on Active Area (AA) solely.
As exposure patterns get smaller and smaller, the requirement for controlling gate dimension is more and more strict and the requirements to photolithography technology and OPC are higher and higher after the dimension of exposure patterns comes to 65 nm-technology. Slight differences among optical effects for different substrates have affected technology window for photolithography and performance of devices.
FIG. 1 is a layout for gate design in background of present invention. FIG. 2 is a simulation graph of gate spacing dimension corrected based on a model of the gate based on the Shallow-trench isolation (STI) in a situation that exposure conditions vary in background of present invention. As shown in FIGS. 1-2, because of small gate (poly) spacing dimension of the STI, line spacing dimension error (Bridge) is likely to occur when photolithography exposure conditions vary. FIG. 3 is a simulation graph of gate spacing dimension corrected based on a model of the gate based on the Active Area (AA) in the situation that exposure conditions vary. As shown in FIG. 3, spacing dimension error (Bridge) also occurs in the condition of only making correction based on the model of the AA. FIG. 4 is a simulation graph of gate characteristic dimension based on different substrate areas in the method of making OPC based on different substrate areas in background of present invention. As shown in FIG. 4, CDs have slight difference for different substrates.
As shown in FIGS. 3-4, in actual layouts, all of line-end spacings are on the STI. According to nowaday practice, OPC is made based on the OPC model of the AA for all patterns, i.e., correction is made by using the OPC model on the AA. Because of correction error caused by different substrates, the spacing dimension error may occur when the photolithography exposure conditions vary.